IIT Delhi Electrical Engineering Researchers Develop India's First Micro-Graphics Processing Unit
IIT Delhi researchers have built India’s first indigenous micro-GPU on a Spartan-7 FPGA to cut reliance on imported GPU chips for embedded displays. Read the article to get more information.
India’s semiconductor journey just gained a new milestone. Researchers at the Electrical Engineering Department of IIT Delhi have developed the country’s first working micro-Graphics Processing Unit. The team calls it the first demonstrably indigenous micro-GPU from an Indian university. GPUs power modern computing hardware everywhere. They also drive artificial intelligence and machine learning systems. This compact chip aims to reduce India’s dependence on imported GPU technology. Scroll to get complete details.
A Fully Indigenous Chip on FPGA Hardware
The work follows an official IIT Delhi release. The team stated that to the best of their knowledge this is the first working and demonstrably indigenous micro-GPU design from an Indian university. The researchers demonstrated programmable graphics rendering with a custom floating point GPU engine. They built the entire engine in Register Transfer Language and mapped it to a Spartan-7 Field Programmable Gate Array platform. The architecture supports indigenous graphics and display processing for embedded applications. It is a scalable programmable graphics processor intellectual property block. It fits industrial control displays low-cost human machine interfaces, e-rickshaw dashboard navigators, inland water navigation terminals for small fishing boats, educational e-book readers and affordable embedded visualisation systems. The design can be mapped to application specific integrated circuits or to programmable hardware such as FPGAs.
Next Steps and the Team Behind It
The team is exploring a roadmap towards an 8-16 core vector style graphics processor architecture. That plan includes an optimised compiler and a graphics software toolchain. They also want a proof of concept on a 65 nm ASIC process node. The researchers believe mature nodes like 65 nm can make indigenous graphics silicon affordable and practical for embedded systems. The team is now seeking funding for ASIC development system integration and commercialisation. MTech students Nammi Akash and Ravi Teja led the project. Professor Jayadeva and Professor Kaushik Saha of the Electrical Engineering Department guided them. In a joint statement the students said their objective was a compact yet genuinely programmable graphics architecture for FPGA implementation and future ASIC realisation. They hope such indigenous hardware supports affordable digital-access platforms and helps bridge the digital divide. They thanked IIT Delhi for the academic environment and the technical platform that enabled this work.
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